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IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: - - - - - - - - - - 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 1.27mm pitch SOIC, 0.65mm pitch SSOP, 0.635mm pitch QSOP, 0.65mm TSSOP packages Extended commercial range of -40C to +85C VCC = 3.3V 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V 0.2V CMOS power levels (0.4 W typ. static) Rail-to-Rail output swing for increased noise margin IDT74ALVCH374 ADVANCE INFORMATION DESCRIPTION: This octal postive edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The ALVCH374 device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH374 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH374 has a "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. Drive Features for ALVCH374: - High Output Drivers: 24mA - Suitable for heavy loads APPLICATIONS: * 3.3V High Speed Systems * 3.3V and lower voltage computing systems Functional Block Diagram OE 1 CLK 11 C1 2 3 1D 1D 1Q TO SEVEN OTHER CHANNELS EXTENDED COMMERCIAL TEMPERATURE RANGE 1 c 1999 Integrated Device Technology, Inc. MARCH 1999 DSC-4473/- IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE EXTENDED COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATING(1) Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND Max. - 0.5 to + 4.6 -0.5 to VCC + 0.5 - 65 to + 150 - 50 to + 50 50 - 50 100 Unit V V C mA mA mA mA ALVC Link OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q 1 2 3 4 5 6 7 8 9 10 SO20-2 SO20-7 SO20-8 SO20-9 20 19 18 17 16 15 14 13 12 11 VCC VTERM(3) 8Q 8D 7D 7Q 6Q 6D 5D 5Q TSTG IOUT IIK IOK ICC ISS GND CLK SSOP/ TVSOP/ TSSOP/ QSOP TOP VIEW NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25C, f = 1.0MHz) PIN DESCRIPTION Pin Names OE CLK xD xQ Description 3-State Output Enable Input (Active LOW) Clock Input Data Inputs(1) 3-State Outputs Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF ALVC Link NOTE: 1. As applicable to the device type. NOTE: 1. These pins have "Bus-hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (each flip=flop) Inputs OE L L L H CLK H or L X xD H L X X (1) Output xQ H L Q0 Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition Q0 = Level of Q before the indicated steady-state input conditions were established. c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7 V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- - 0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 - 1.2 -- 10 A A V mV A A V Unit V Quiescent Power Supply Current Variation -- -- 750 A ALVC Link NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient. ALVC Link Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3.0V VCC = 2.3V VCC = 3.6V Test Conditions VI = 2.0V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V Min. - 75 75 - 45 45 -- Typ.(2) -- -- -- -- -- Max. -- -- -- -- 500 Unit A A A 3 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 ALVC Link Unit V V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C. OPERATING CHARACTERISTICS, TA = 25oC VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical VCC = 3.3V 0.3V Typical Unit pF pF SWITCHING CHARACTERISTICS (1) VCC = 2.5V 0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tW tSU tH tSK(o) Parameter Propagation Delay CLK to xQ Output Enable Time OE to xQ Output Disable Time OE to xQ Pulse Duration, CLK HIGH or LOW Setup Time, data before CLK Hold Time, data after CLK Output Skew(2) Min. -- -- -- 3.3 2 1.5 -- Max. 8 8.5 9.5 -- -- -- -- VCC = 2.7V Min. -- -- -- 3.3 2 1.5 -- Max. 7 7.5 6.5 -- -- -- -- VCC = 3.3V 0.3V Min. 2.2 1.5 1.5 3.3 2 1.5 -- Max. 6 6.5 5.5 -- -- -- 500 Unit ns ns ns ns ns ns ps NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc VCC / 2 150 150 30 V V mV mV pF ALVC Link SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL VIH VT 0V VOH VT VOL VIH VT 0V ALVC Link TEST CIRCUITS FOR ALL OUTPUTS VCC 500 Pulse Generator (1, 2) VLOAD Open GND ENABLE AND DISABLE TIMES ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLO SED LOW tPZH OUTPUT SW ITCH NORMALLY OP EN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V ALVC Link VIN D.U.T. VOUT RT 500 CL ALVC Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. SET-UP, HOLD, AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD tSU tH GND Open ALVC Link tSU OUTPUT SKEW INPUT tPLH1 TSK (x) tPHL1 tH VIH VT 0V VOH PULSE WIDTH LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE VT A LV C Link OUTPUT 1 tSK (x) tSK (x) VT VOL VOH VT OUTPUT 2 tPLH2 tPHL2 VT VOL tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. ALVC Link 5 IDT74ALVCH374 3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX ALVC X XXX Device Type XX Package Temp. Range Bus-Hold SO PY Q PG Small Outline IC (SO 20-2) Shrink S m all Outline Package (SO20-7) Quarter-size Sm all Outline Package (SO20-8) Thin Shrink Small Outline Package (SO20-9) Octal Positive Edge-Triggered D-Type Flip-Flop with 3-State Outputs, 24mA Bus-Hold -40C to +85C 374 H 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6 |
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